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w83194r - 67b 100mhz 3 - dimm clo ck for via mvp4 publication release date: dec . 1999 - 1 - revision 0. 5 0 1.0 general descrip tion the w83194r - 67b is a clock synthesizer which provides all clocks required for high - speed risc or cisc microprocessor such as intel pentium , amd and cyrix. w83194r - 67b provides sixteen cpu/pci frequencies which are externally sel ectable with smooth transitions. w83194r - 67b also provides 13 sdram clocks controlled by the none - delay buffer_in pin. the w83194r - 67b accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. spread spectrum built in at 0.5% or 0. 25% to reduce emi. programmable stopping individual clock outputs and frequency selection through i 2 c interface. the device meets the pentium power - up stabilization, which requires cpu and pci clocks be stable within 2 ms after power - up. high drive si x pci and thirteen sdram clock outputs typically provide greater than 1 v /ns slew rate into 30 pf loads. two cpu clock outputs typically provide better than 1 v /ns slew rate into 20 pf loads as maintaining 50 5% duty cycle. the fixed frequency output s as ref, 24mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2.0 product feature s supports pentium ? , amd, cyrix cpu with i 2 c. 4 cpu clocks (one free - running cpu clock) 13 sdram clocks for 3 dims 6 pci synchronous clocks optional single or mixe d supply: (vddq1=vddq2 = vddq3 = vddq4 = vddl1 =vddl2= 3.3v) or (vddq1= vddq2 = vddq3=vddq4 = 3.3v, vddl1 = vdql2 = 2.5v) < 250ps skew among cpu and sdram clocks < 4ns propagation delay sdram from buffer input skew from cpu(earlier) to pci cl ock - 1 to 4ns, center 2.6ns. smooth frequency switch with selections from 60 mhz to 124 mhz cpu i 2 c 2 - wire serial interface and i 2 c read back 0~0.5% down type or 0.25% or 0.5% spread spectrum function to reduce emi programmable registers to enable/st op each output and select modes (mode as tri - state or normal ) 2ms power up clock stable time mode pin for power management one 48 mhz for usb & one 24 mhz for super i/o packaged in 48 - pin ssop
w83194r - 67b preliminary publication release date: dec. . 1999 - 2 - revision 0. 5 0 3.0 block diagram pll2 xtal osc spread spectrum pll1 latch por stop 1/2 control logic config. reg. stop stop pci clock divider ~ ~ 4 2 12 5 48mhz 24mhz ref(0:1) cpuclk_f cpuclk(0:2) sdram(0:11) pciclk(0:4) pciclk_f xin xout buffer in fs(0:3)* 4 mode* *cpu_stop# *pci_stop# sdata* sdclk* sdram_f 3 4.0 pin configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vddq1 * pci_stop#/ref0 vss xin xout vddq2 pciclk_f/ *mode pciclk0/ *fs3 vss pciclk1 pciclk2 pciclk3 pciclk4 vddq2 buffer in vss sdram11 sdram10 vddq3 sdram 9 sdram 8 vss *sdata *sclk vddl1 ref1/ *fs2 vss cpuclk_f cpuclk0 *cpu_stop# sdram_f vss sdram 0 sdram 1 sdram 2 vddq3 sdram 3 vss sdram 4 sdram 5 sdram 6 sdram 7 vddq4 vddq3 48mhz/ *fs0 24mhz/ *fs1 cpuclk1 cpuclk2
w83194r - 67b preliminary publication release date: dec. . 1999 - 3 - revision 0. 5 0 5.0 pin description in - input out - output i/o - bi - directional pin # - active low * - internal 250k w pull - up 5.1 crystal i/o symbol pin i/o function xin 4 in crystal input with internal loading capacitors and f eedback resistors. xout 5 out crystal output at 14.318mhz nominally. 5.2 cpu, sdram, pci, ioapic clock outputs symbol pin i/o function cpuclk_f 46 out free running cpu clock. not affected by cpu_stop# cpuclk[0:2] 45,43,42 out low skew (< 250ps) cloc k outputs for host frequencies such as cpu, chipset and cache. powered by vddl2. low if cpu_stop# is low. *cpu_stop# 41 in this asynchronous input halts cpuclk[0:2] and sdram(0:11) at logic level when driven low. sdram_f 39 out free running sdram clo ck. not affected by cpu_stop# sdram [ 0:11] 17,18,20,21,28 ,29,31,32,34, 35,37,38 out sdram clock outputs. fanout buffer outputs from buffer in pin.(controlled by chipset) pciclk_f/ *mode 7 i/o free running pci clock during normal operation. latched inp ut. mode=1, pin 2 is ref0; mode=0, pin2 is pci_stop# pciclk0/*fs3 8 i/o low skew (< 250ps) pci clock outputs. latched input for fs3 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. pciclk [ 1:4 ] 10 ,11,12,13 out low skew (< 250ps) pci clock outputs. synchronous to cpu clocks with 1/ - 4ns skew(cpu early). buffer in 15 in inputs to fanout for sdram outputs.
w83194r - 67b preliminary publication release date: dec. . 1999 - 4 - revision 0. 5 0 5.3 i 2 c control interface symbol pin i/o function *sdata 23 i/o serial data of i 2 c 2 - wire control interface with internal pull - up resistor. *sdclk 24 in serial clock of i 2 c 2 - wire control interface with internal pull - up resistor. 5.4 fixed frequency outputs symbol pin i/o function ref0 / *pci_stop# 2 i/o 14.318mhz reference clock. this ref output is the stronger buffer for isa bus loads. halt pciclk(0:4) clocks at logic 0 level, when input low (in mobile mode. mode=0) ref1 / *fs2 48 i/o 14.318mhz reference clock. latched input for fs2 at initial power up for h/w selecting the output freque ncy of cpu, sdram and pci clocks. 24mhz / *fs1 25 i/o 24mhz output clock. latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 48mhz / *fs0 26 i/o 48mhz output for usb during normal operation. lat ched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 5.5 power pins symbol pin function vddq1 1 power supply for ref [0:1] , xin and xout crystal. vddl1 47 power supply for cpu clock outputs, ei ther 2.5v or 3.3v. vddq2 6, 14 power supply for pciclk_f, pciclk[1:4], 3.3v. vddq3 19, 30, 36 power supply for sdram_f,sdram[0:11], and pll core, nominal 3.3v. vddq4 27 power for 24 & 48mhz output buffers and pll core. vss 3,9,16,22,33,40,44 circuit ground.
w83194r - 67b preliminary publication release date: dec. . 1999 - 5 - revision 0. 5 0 6.0 frequency selec tion fs3 fs2 fs1 fs0 cpu,sdram(mhz) pci(mhz) ref,ioapic (mhz) 1 1 1 1 60 30(cpu/2) 14.318 1 1 1 0 66.8 33.4(cpu/2) 14.318 1 1 0 1 70 35(cpu/2) 14.318 1 1 0 0 90 30(cpu/3) 14.318 1 0 1 1 97.0 32.33(cpu/3) 14.318 1 0 1 0 83.3 27.77(cpu/3) 14.318 1 0 0 1 95.25 31.75(cpu/3) 14.318 1 0 0 0 100.2 33.3(cpu/3) 14.318 0 1 1 1 75 37.5(cpu/2) 14.318 0 1 1 0 80 40(cpu/2) 14.318 0 1 0 1 83.3 41.65(cpu/2) 14.318 0 1 0 0 105 35(cpu/3) 14.318 0 0 1 1 110 36.67(cpu/3) 14.318 0 0 1 0 115 38.33(cpu/3) 14.318 0 0 0 1 124 31(cpu/4) 14.318 0 0 0 0 133 33.3(cpu/4) 14.318 7.0 mode pin - power management input co ntrol mode, pin7 (latched input) pin 2 0 pci_stop# (input) 1 ref0 (output)
w83194r - 67b preliminary publication release date: dec. . 1999 - 6 - revision 0. 5 0 8.0 function descri ption 8.1 power manag ement functions all clocks can be individually enabled or disabled via the 2 - wire control interface. on power up, external circuitry should allow 3 ms for the vco? to stabilize prior to enabling clock outputs to assure correct pulse widths. when mode=0, pins 15 and 46 are inputs (pci_stop#), (cpu_stop#), when mode=1, these functions are not available. a particular clock could be enabled as both the 2 - wire serial control interface and one of these pins indicate that it should be enable. the w83194r - 67b may be disabled in the low state according to the following table in order to reduce power consumption. all clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. the cpu and pci clocks transform betwe en running and stop by waiting for one positive edge on pciclk_f followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. cpu_stop# pci_stop# cpuclk 0:2, sdram 0:11 pci sdram_f, cpu_f,pci _f other clks 0 0 low low running running 0 1 low running running running 1 0 running low running running 1 1 running running running running 8.2 2 - wire i 2 c control interface the clock generator is a slave i 2 c component which can be read back? th e data stored in the latches for verification. all proceeding bytes must be sent to change one of the control bytes. the 2 - wire control interface allows each clock output individually enabled or disabled. on power up, the w83194r - 67b initializes with de fault register settings, and then it is optional to use the 2 - wire control interface. the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high during normal data transfer. there are only two exceptions. one is a high - to - low transition on sdata while sdclk is high used to indicate the beginning of a data transfer cycle. the other is a low - to - high transition on sdata while sdclk is high used to indicate the end of a data transfer cycle. data is always sent as complete 8 - bit bytes followed by an acknowledge generated. byte writing starts with a start condition followed by 7 - bit slave address and a write command bit [1101 0010], command code checking [0000 0000], and byte count checking. after successful reception of e ach byte, an acknowledge (low) on the sdata wire will be generated by the clock chip. controller can start to write to internal i 2 c registers after the string of data. the sequence order is as follows:
w83194r - 67b preliminary publication release date: dec. . 1999 - 7 - revision 0. 5 0 bytes sequence order for i 2 c controller : clock address a(6:0) & r/w ack 8 bits dummy command code ack 8 bits dummy byte count ack byte0,1,2... until stop set r/w to 1 when read back the data sequence is as follows : clock address a(6:0) & r/w ack byte 0 ack ack byte2, 3, 4... until stop byte 1 8.3 serial control registers the pin column lists the affected pin number and the @powerup column gives the default state at true p ower up. "command code" byte and "byte count" byte must be sent following the acknowledge of the address byte. although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. after that, the below d escribed sequence (register 0, register 1, register 2, ....) will be valid and acknowledged. 8.3.1 register 0: cpu frequency select register (default = 0) bit @powerup pin description 7 0 - 0 = 0.25% center type spread spectrum modulation 1 = 0.5% cen ter type spread spectrum modulation 6 0 - ssel2 (for frequency table selection by software via i 2 c) 5 0 - ssel1 (for frequency table selection by software via i 2 c) 4 0 - ssel0 (for frequency table selection by software via i 2 c) 3 0 - 0 = selection by hardware 1 = selection by software i 2 c - bit 2, 6:4 2 0 - ssel3 (for frequency table selection by software via i 2 c) 1 0 - 0 = normal 1 = spread spectrum enabled 0 0 - 0 = running 1 = tristate all outputs
w83194r - 67b preliminary publication release date: dec. . 1999 - 8 - revision 0. 5 0 frequency table by i2c ssel3 ssel2 ssel1 ssel 0 cpu,sdra m(mhz) pci(mhz) ref,ioapic (mhz) 1 1 1 1 60 30(cpu/2) 14.318 1 1 1 0 66.8 33.4(cpu/2) 14.318 1 1 0 1 70 35(cpu/2) 14.318 1 1 0 0 90 30(cpu/3) 14.318 1 0 1 1 97.0 32.33(cpu/3) 14.318 1 0 1 1 80 26.67(cpu/3) 14.318 1 0 1 0 83.3 27.77(cpu/3) 14.318 1 0 0 1 95.25 31.75(cpu/3) 14.318 1 0 0 0 100.2 33.3(cpu/3) 14.318 0 1 1 1 75 37.5(cpu/2) 14.318 0 1 1 0 80 40(cpu/2) 14.318 0 1 0 1 83.3 41.65(cpu/2) 14.318 0 1 0 0 105 35(cpu/3) 14.318 0 0 1 1 110 36.67(cpu/3) 14.318 0 0 1 0 115 38.33(cpu/ 3) 14.318 0 0 0 1 124 31(cpu/4) 14.318 0 0 0 0 133 33.3(cpu/4) 14.318 8.3.2 register 1 : cpu clock register (1 = active, 0 = inactive) bit @powerup pin description 7 x - latched fs2# 6 1 - 0 = 0.5% down type spread, overrides byte0 - bit7. 1= center type spread. 5 1 - reserved 4 1 - reserved 3 1 42 cpuclk2 (active / inactive) 2 1 43 cpuclk1 (active / inactive) 1 1 45 cpuclk0 (active / inactive) 0 1 46 cpuclk_f (active / inactive)
w83194r - 67b preliminary publication release date: dec. . 1999 - 9 - revision 0. 5 0 8.3.3 register 2: pci clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 - reserved 6 1 7 pciclk_f (active / inactive) 5 1 - reserved 4 1 13 pciclk4 (active / inactive) 3 1 12 pciclk3 (active / inactive) 2 1 11 pciclk2 (active / inactive) 1 1 10 pciclk1 (active / inactive) 0 1 8 pciclk0 (active / inactive) 8.3.4 register 3: sdram clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 - reserved 6 x - latched fs0# 5 1 26 48mhz (active / inactive) 4 1 25 24mhz (active / inactive) 3 1 39 sdram_f(active / inactive) 2 1 21,20,18,17 sdram(8:11) (active / inactive) 1 1 32,31,29,28 sdram(4:7) (active / inactive) 0 1 38,37,35,34 sdram(0:3) (active / inactive) 8.3.5 register 4: reserved register (1 = active, 0 = inactive) bit @powerup pin description 7 1 - reserved 6 1 - reserved 5 1 - reserved 4 1 - reserved 3 x - latched fs1# 2 1 - reserved 1 x - latched fs3# 0 1 - reserved
w83194r - 67b preliminary publication release date: dec. . 1999 - 10 - revision 0. 5 0 8.3.6 register 5: peripheral control (1 = active, 0 = inactive) bit @powerup pin description 7 1 - reserved 6 1 - reserved 5 1 - rese rved 4 1 - reserved 3 1 - reserved 2 1 - reserved 1 1 48 ref1 (active / inactive) 0 1 2 ref0 (active / inactive) 8.3.7 register 6: winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 0 - winbond chip id 4 1 - winbond chip id 3 1 - winbond chip id 2 0 - winbond chip id 1 0 - winbond chip id 0 0 - winbond chip id note: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects(fs#) will be inver ted logic load of the input frequency select pin conditions.
w83194r - 67b preliminary publication release date: dec. . 1999 - 11 - revision 0. 5 0 9.0 specifications 9.1 absolute maximum ratings stresses greater than those listed in this table may cause permanent damage to the device. precautions should be taken to avoid applica tion of any voltage higher than the maximum rated voltages to this circuit. maximum conditions for extended periods may affect reliability. unused inputs must always be tied to an appropriate logic voltage level (ground or vdd). symbol parameter rating vdd , v in voltage on any pin with respect to gnd - 0.5 v to + 7.0 v t stg storage temperature - 65 c to + 150 c t b ambient temperature - 55 c to + 125 c t a operating temperature 0 c to + 70 c 9.2 ac characteristics vddq1=vddq2 = vddq3 = vddq4 =3.3v , vddl1 =vddl2= 2.5v , t a = 0 c to +70 c parameter symbol min typ max units test conditions output duty cycle 45 50 55 % measured at 1.5v cpu/sdram to pci offset t off 1 4 ns 15 pf load measured at 1.5v skew (cpu - cpu), (pci - pci), (sdram - sdram) t skew 2 50 ps 15 pf load measured at 1.5v cpu/sdram cycle to cycle jitter t ccj 250 ps cpu/sdram absolute jitter t ja 500 ps jitter spectrum 20 db bandwidth from center bw j 500 khz output rise (0.4v ~ 2.0v) & fall (2.0v ~0.4v) time t tlh t thl 0.4 1.6 ns 15 pf load on cpu and pci outputs overshoot/undershoot beyond power rails v over 1.5 v 22 w at source of 8 inch pcb run to 15 pf load ring back exclusion v rbe 2.1 v ring back must not enter this range.
w83194r - 67b preliminary publication release date: dec. . 1999 - 12 - revision 0. 5 0 9.3 dc characteristics vddq1=vddq2 = vddq 3 = vddq4 =3.3v, vddl1 =vddl2= 2.5v , t a = 0 c to +70 c parameter symbol min typ max units test conditions input low voltage v il 0.8 v dc input high voltage v ih 2.0 v dc input low current i il - 66 m a input high current i ih 5 m a output low vo ltage i ol = 4 ma v ol 0.4 v dc all outputs output high voltage i oh = 4ma v oh 2.4 v dc all outputs using 3.3v power tri - state leakage current ioz 10 m a dynamic supply current for vdd + vddq3 i dd3 ma cpu = 66.6 mhz pci = 33.3 mhz with load dynami c supply current for vddq2 + vddq2b i dd2 ma same as above cpu stop current for vdd + vddq3 i cpus3 ma same as above cpu stop current for vddq2 + vddq2b i cpus2 ma same as above pci stop current for vdd + vddq3 i pd3 ma
w83194r - 67b preliminary publication release date: dec. . 1999 - 13 - revision 0. 5 0 9.4 buf fer characteristics 9.4.1 type 1 buffer for cpu clock parameter symbol min typ max units test conditions pull - up current min i oh(min) - 27 ma vout = 1.0 v pull - up current max i oh(max) - 27 ma vout = 2.0v pull - down current min i ol(min) ma vout = 1. 2 v pull - down current max i ol(max) 27 ma vout = 0.3 v rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 1.6 ns 20pf load 9.4.2 type 3 buffer for ref[0:1], 24mhz, 48mhz parame ter symbol min typ max units test conditions pull - up current min i oh(min) - 29 ma vout = 1.0 v pull - up current max i oh(max) - 23 ma vout = 3.135v pull - down current min i ol(min) 29 ma vout = 1.95 v pull - down current max i ol(max) ma vout = 0.4 v rise/fall time min between 0.8 v and 2.0 v t rf(min) 1.0 ns 10pf load rise/fall time max between 0.8 v and 2.0 v t rf(max) 4.0 ns 20pf load 9.4.3 type 4 buffer for sdram (f,0:11) parameter symbol min typ max units test conditions pull - up current min i oh(min) ma vout = 1.65 v pull - up current max i oh(max) - 46 ma vout = 3.135 v pull - down current min i ol(min) ma vout = 1.65 v pull - down current max i ol(max) 53 ma vout = 0.4 v rise/fall time min between 0.8 v and 2.0 v t rf(min) 0.5 ns 20pf load rise/fall time max between 0.8 v and 2.0 v t rf(max) 1.3 ns 30pf load
w83194r - 67b preliminary publication release date: dec. . 1999 - 14 - revision 0. 5 0 9.4.4 type 5 buffer for pciclk(0:4,f) parameter symbol min typ max units test conditions pull - up current min i oh(min) - 33 ma vout = 1.0 v pull - up current max i oh(max) - 3 3 ma vout = 3.135 v pull - down current min i ol(min) 30 ma vout = 1.95 v pull - down current max i ol(max) 38 ma vout = 0.4 v rise/fall time min between 0.8 v and 2.0 v t rf(min) 0.5 ns 15pf load rise/fall time max between 0.8 v and 2.0 v t rf(max) 2. 0 ns 30pf load
w83194r - 67b preliminary publication release date: dec. . 1999 - 15 - revision 0. 5 0 10.0 power manageme nt timing 10.1 cpu_stop# timing diagram cpuclk (internal) pciclk (internal) pciclk_f cpu_stop# cpuclk[0:3] sdram 3 4 1 2 3 4 1 2 for synchronous chipset, cpu_stop# pin is an asynchronous ? active low ? input pin used to stop the cpu clocks for low power operation. this pin is asserted synchronously b y the external control logic at the rising edge of free running pci clock(pciclk_f). all other clocks will continue to run while the cpu clocks are stopped. the cpu clocks will always be stopped in a low state and resume output with full pulse width. in this case, cpu ?locks on latency ? is less than 4 cpu clocks and ?locks off latency ? is less then 4 cpu clocks. 10.2 pci_stop# timing diagram cpuclk (internal) pciclk (internal) pciclk_f pci_stop# pciclk[0:5] 1 2 1 2 for synchronous chipset, pci_stop# pin is an asynchronous ?ctive low ? input pin used to stop th e pciclk [0:4] for low power operation. this pin is asserted synchronously by the external control logic at the rising edge of free running pci clock(pciclk_f). all other clocks will continue to run while the pci clocks are stopped. the pci clocks wi ll always be stopped in a low state and resume output with full pulse width. in this case, pci ?locks on latency ? is less than 2 pci clocks and ?locks off latency ? is less then 2 pci clocks.
w83194r - 67b preliminary publication release date: dec. . 1999 - 16 - revision 0. 5 0 11.0 operation of d ual fuction pins device pin vdd ground ground 10k series terminating resistor clock trace emi reducing cap 10k w w optional device pin vdd pad ground pad programming header series terminating resistor clock trace emi reducing cap ground 10k w optional
w83194r - 67b preliminary publication release date: dec. . 1999 - 17 - revision 0. 5 0 12.0 ordering infor mation part number package type production flow w83194r - 67b 48 pin ssop commercial, 0 c to +70 c 13.0 how to read th e top marking 1st line: winbond logo and the type number: w83194r - 67b 2nd lin e: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 002 g a b 002 : packages made in ' 00 , week 02 g : assembly house id; a means ase, s means spil, g means gr a b : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . w83194r - 67b 28051234 002 gab - 10
w83194r - 67b preliminary publication release date: dec. . 1999 - 18 - revision 0. 5 0 14.0 package drawin g and dimensions headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support appliances, devices, or system s where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resu lting from such improper use or sale.

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